Contact: Carlo Reita (firstname.lastname@example.org)
The Fully Depleted Silicon thin films technology On Insulator (FDSOI) exhibits major benefits for advanced and future technological nodes. Thin silicon films technology allows an electrostatic control by the gate on the channel of the transistor which is largely better compared to conventional architectures. This excellent electrostatic control allows a better compromise between performances and power consumption at circuit level, and offers a great potential in term of scaling of logic circuits in particular for mobile applications.
Compared to the FinFET, an alternative technology which also allows a good electrostatic control, the FDSOI remains a planar technology and so makes easier the transition from conventional technologies. In this sense, FDSOI manufacturability is largely simplified compared to FinFET.
The use of thin buried insulator layers in FDSOI (hence the name Ultra-Thin Body and Box technology for this variant) offers the capability to dynamically modulate the threshold voltage of the devices and so obtaining the best compromise at any time between performances and power consumption. This modulation is obtained at circuit level by back biasing the rear face of the transistors through the insulator layer and so allowing the designers to adapt in real time the power consumption of the circuit depending on its operation regime.
The Leti-UTSOI compact model was developed to describe the electrical behavior of FDSOI transistor taking into account all its specificities. The model is based on a physical description of the device and all the parameters are physically based, allowing its use also for predictive analysis of the process. The electrostatic coupling between the front and rear interfaces of the thin silicon film is part of the model and so it is particularly adapted to represent the behaviour of the devices in low doped thin silicon technologies in a large range of insulator layer thicknesses (from nanometers to hundreds of micrometers).
In its latest version (2.0), the Leti-UTSOI compact model includes the full description of the creation of an inversion layer at the rear face of the silicon film. This physical description is based on an original and non-simplified resolution of the equations which govern the electrostatics of the transistor. The Leti-UTSOI model is the first and unique compact model exhibiting this capability and so able to describe transistor behaviours in a large range of polarization applied both at the front and at the rear interface of the transistor.
The developments of the Leti-UTSOI model is based on a large range of competences and of technological capabilities bring together in CEA-Leti which is part of the Minatec campus. Based on a long time experience in SOI technology development, the CEA-Leti has built a unique and large range of expertise from materials integration to IC design through process integration development, multi-scale chemical and physical characterization, fine electrical characterization of devices and numerical simulation calibrated on state-of-the art process and device data.
In the framework of its collaborations with industrial partners, the CEA-Leti continuously grows its expertise on the more advanced technologies. It confers to the CEA-Leti a complete and unique expertise of the physical understanding of the electrical behavior of the FDSOI transistor which is the foundation of our compact model development activity and more particularly of the development of the Leti-UTSOI model.
In its version 1.14, the Leti-UTSOI model has reached its maturity. In collaboration with STMicroelectronics, its robustness was validated by successfully complying with the full test suite recommended by the Compact Model Council. The Leti-UTSOI model is now currently used at STMicroelectronics in the design division.
Quotes from STMicroelectronics designers:
“Thanks to the UTSOI model from CEA-Leti, STMicroelectronics has developed a complete design platform for SOC including a full set of libraries and its associated design flow. This model is supported in all the major spice simulators from the industry such as HSPICE, ELDO or SPECTRE and can be easily implemented within a conventional design flow as conceived for bulk.”
“This compact model has been clearly developed with the objective to meet the present and future needs of circuit designers, with the capability to accurately reflect the transistor behavior down to 10nm and below on wide ranges of body bias, poly bias and supply voltage. Thanks to this approach, it provides circuit designers a key advantage for digital and analog research as well as technology benchmarking from the early stage of the development of a new node. UTSOI appears the must-have solution for high performance and low power circuit simulations in UTBB FD-SOI.”
The Leti-UTSOI compact model is the only one to be totally dedicated to the FDSOI technology. It is now available in an industrial design-kit. The documentation and some model cards (typical) are available below :
The Verilog-A code can also be obtained : please contact us !
If you are particularly interested in the FDSOI technology and its possible applications, the CEA-Leti can help you by:
- analyzing and quantifying the advantages of the FDSOI technology for your specific needs
- accelerating your technological developments and circuit designs
- supporting you in electrical and physical characterization, numerical simulation and modeling.